diff options
Diffstat (limited to 'src/soc/intel/common/block')
4 files changed, 5 insertions, 27 deletions
diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index bd248d338b..826e718da8 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -34,9 +34,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume - E4GM, 8, // 0x30 - Enable above 4GB MMIO Resource - A4GB, 64, // 0x31 - 0x38 Base of above 4GB MMIO Resource - A4GS, 64, // 0x39 - 0x40 Length of above 4GB MMIO Resource + A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource + A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h index 621f0586cb..be2af4aeab 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfg.h +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -24,7 +24,6 @@ struct soc_intel_common_config { /* PCH Thermal Trip Temperature in deg C */ uint8_t pch_thermal_trip; struct mmc_dll_params emmc_dll; - int enable_above_4GB_mmio; }; /* This function to retrieve soc config structure required by common code */ diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 003a608f76..e1040eac3c 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -25,10 +25,9 @@ typedef struct global_nvs_t { u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ u8 uior; /* 0x2f - UART debug controller init on S3 resume */ - u8 e4gm; /* 0x30 - Enable above 4GB MMIO Resource */ - u64 a4gb; /* 0x31 - 0x38 Base of above 4GB MMIO Resource */ - u64 a4gs; /* 0x39 - 0x40 Length of above 4GB MMIO Resource */ - u8 unused[191]; + u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */ + u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */ + u8 unused[192]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 3da837c0af..7355817ec2 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -96,30 +96,11 @@ static void sa_read_map_entry(struct device *dev, *result = value; } -/* - * This function will get above 4GB mmio enable config specific to soc. - * - * Return values: - * 0 = Above 4GB memory is not enable - * 1 = Above 4GB memory is enable - */ -static int get_enable_above_4GB_mmio(void) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - - return common_config->enable_above_4GB_mmio; -} - /* Fill MMIO resource above 4GB into GNVS */ void sa_fill_gnvs(global_nvs_t *gnvs) { - if (!get_enable_above_4GB_mmio()) - return; - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - gnvs->e4gm = 1; sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb); gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE; printk(BIOS_DEBUG, "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n", |