diff options
Diffstat (limited to 'src/soc/intel/common/block/systemagent/systemagent.c')
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent.c | 25 |
1 files changed, 3 insertions, 22 deletions
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 0312cac94e..e03942fb30 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -46,11 +46,6 @@ __weak int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, return -1; } -__weak size_t soc_reserved_mmio_size(void) -{ - return 0; -} - __weak unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, struct acpi_rsdp *rsdp) @@ -125,8 +120,7 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values) * These are the host memory ranges that should be added: * - 0 -> 0xa0000: cacheable * - 0xc0000 -> top_of_ram : cacheable - * - top_of_ram -> TSEG - DPR: uncacheable - * - TESG - DPR -> BGSM: cacheable with standard MTRRs and reserved + * - top_of_ram -> BGSM: cacheable with standard MTRRs and reserved * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved * - 4GiB -> TOUUD: cacheable * @@ -155,18 +149,11 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values) static void sa_add_dram_resources(struct device *dev, int *resource_count) { uintptr_t base_k, touud_k; - size_t dpr_size = 0, size_k; - size_t reserved_mmio_size; + size_t size_k; uint64_t sa_map_values[MAX_MAP_ENTRIES]; uintptr_t top_of_ram; int index = *resource_count; - if (CONFIG(SA_ENABLE_DPR)) - dpr_size = sa_get_dpr_size(); - - /* Get SoC reserve memory size as per user selection */ - reserved_mmio_size = soc_reserved_mmio_size(); - top_of_ram = (uintptr_t)cbmem_top(); /* 0 - > 0xa0000 */ @@ -181,14 +168,8 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count) sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> TSEG - DPR - Intel Reserve Memory Size*/ + /* top_of_ram -> BGSM */ base_k = top_of_ram; - size_k = sa_map_values[SA_TSEG_REG] - dpr_size - base_k - - reserved_mmio_size; - mmio_resource(dev, index++, base_k / KiB, size_k / KiB); - - /* TSEG - DPR - Intel Reserve Memory Size -> BGSM */ - base_k = sa_map_values[SA_TSEG_REG] - dpr_size - reserved_mmio_size; size_k = sa_map_values[SA_BGSM_REG] - base_k; reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); |