diff options
Diffstat (limited to 'src/soc/intel/common/block/pmc')
| -rw-r--r-- | src/soc/intel/common/block/pmc/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/common/block/pmc/pmclib.c | 2 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index 46f134e3b1..2f0840847b 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -37,3 +37,11 @@ config PMC_INVALID_READ_AFTER_WRITE help Enable this for PMC devices where a read back of ACPI BAR and IO access bit does not return the previously written value. + +config PMC_GLOBAL_RESET_ENABLE_LOCK + bool + help + Enable this for PMC devices where the reset configuration + and lock register is located under PMC BASE at offset ETR. + Note that the reset register is still at 0xCF9 this only + controls the enable and lock feature. diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 339e674a6e..52bfaecd3d 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -419,6 +419,7 @@ int pmc_fill_power_state(struct chipset_power_state *ps) return ps->prev_sleep_state; } +#if IS_ENABLED(CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK) /* * If possible, lock 0xcf9. Once the register is locked, it can't be changed. * This lock is reset on cold boot, hard reset, soft reset and Sx. @@ -451,6 +452,7 @@ void pmc_global_reset_enable(bool enable) reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; write32((void *)etr, reg); } +#endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK int vboot_platform_is_resuming(void) { |