diff options
Diffstat (limited to 'src/soc/intel/common/block/pmc')
| -rw-r--r-- | src/soc/intel/common/block/pmc/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/intel/common/block/pmc/pmclib.c | 16 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index 3aa0da8b1e..ce41b23620 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -29,3 +29,9 @@ config PMC_GLOBAL_RESET_ENABLE_LOCK and lock register is located under PMC BASE at offset ETR. Note that the reset register is still at 0xCF9 this only controls the enable and lock feature. + +config PMC_LOW_POWER_MODE_PROGRAM + bool + help + Enable this for PMC devices to perform registers programming + to ensure low power in active idle scenario. diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index ad9c4fec3d..8825bbe441 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -700,3 +700,19 @@ uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, return PCH_PM_PWR_CYC_DUR; } + +#if CONFIG(PMC_LOW_POWER_MODE_PROGRAM) +void pmc_disable_acpi_timer(void) +{ + uint8_t *pmcbase = pmc_mmio_regs(); + + setbits8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); +} + +void pmc_ignore_xtal_shutdown(void) +{ + uint8_t *pmcbase = pmc_mmio_regs(); + + setbits8(pmcbase + CPPMVRIC, XTALSDQDIS); +} +#endif /* PMC_LOW_POWER_MODE_PROGRAM */ |