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Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cpulib.h3
-rw-r--r--src/soc/intel/common/block/include/intelblocks/msr.h2
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index 8630fd1eb5..1aa88e156d 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -161,4 +161,7 @@ uint32_t cpu_get_max_turbo_ratio(void);
/* Configure Machine Check Architecture support */
void mca_configure(void);
+/* Lock chipset memory registers to protect SMM */
+void cpu_lt_lock_memory(void *unused);
+
#endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 6fdf26e202..3e67fd779d 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -67,6 +67,8 @@
#define MSR_POWER_CTL 0x1fc
#define POWER_CTL_C1E_MASK (1 << 1)
#define MSR_EVICT_CTL 0x2e0
+#define MSR_LT_CONTROL 0x2e7
+#define LT_CONTROL_LOCK_BIT (0)
#define MSR_SGX_OWNEREPOCH0 0x300
#define MSR_SGX_OWNEREPOCH1 0x301
#define SMM_FEATURE_CONTROL_MSR 0x4e0