diff options
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks/uart.h')
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/uart.h | 56 |
1 files changed, 44 insertions, 12 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index 78feb3e246..545e158b61 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,14 +17,31 @@ #define SOC_INTEL_COMMON_BLOCK_UART_H #include <arch/io.h> +#include <console/uart.h> #include <device/device.h> +#include <intelblocks/gpio.h> #include <stdint.h> +#define MAX_GPIO_PAD_PER_UART 2 + +struct uart_gpio_pad_config { + int console_index; + struct pad_config gpios[MAX_GPIO_PAD_PER_UART]; +}; + +/* + * While using this common UART block for any SOC following is expected from soc + * 1. SOC will define proper UART_BASE which is base address for UART console. + * 2. SOC will return correct device pointer based on console index + * 3. SOC will provide appropriate GPIO pad configuration for UART console + * 4. SOC will allow common code to set UART into legacy mode if supported. + */ + /* * Common routine to initialize UART controller PCI config space, take it out of * reset and configure M/N dividers. */ -void uart_common_init(device_t dev, uintptr_t baseaddr); +void uart_common_init(struct device *dev, uintptr_t baseaddr); /* * Check if UART debug controller is initialized @@ -33,7 +50,7 @@ void uart_common_init(device_t dev, uintptr_t baseaddr); * out of reset * false = otherwise */ -bool uart_debug_controller_is_initialized(void); +bool uart_is_controller_initialized(void); /* * Check if dev corresponds to UART debug port controller. @@ -44,26 +61,41 @@ bool uart_debug_controller_is_initialized(void); */ bool uart_is_debug_controller(struct device *dev); -/**************************** SoC callbacks ***********************************/ - -void pch_uart_read_resources(struct device *dev); +/* + * BootBlock pre initialization of UART console + */ +void uart_bootblock_init(void); /* - * Check if UART debug port controller needs to be initialized on resume. + * Get UART debug controller device structure * * Returns: - * true = when SoC wants common code to do the UART debug port initialization - * false = otherwise + * Pointer to device structure = If device has a UART debug controller. + * NULL = otherwise */ -bool pch_uart_init_debug_controller_on_resume(void); +struct device *uart_get_device(void); + +/**************************** SoC callbacks ***********************************/ /* - * Get UART debug controller device structure + * SoC should implement soc_uart_console_to_device() function to + * get UART debug controller device structure based on console number + * Caller needs to check proper UART console index supported by SoC. + * If wrong UART console index is passed to function, it'll return NULL. + * + * Input: + * UART console index selected in config * * Returns: * Pointer to device structure = If device has a UART debug controller. * NULL = otherwise */ -device_t pch_uart_get_debug_controller(void); +struct device *soc_uart_console_to_device(int uart_console); + +/* + * Set UART to legacy mode + * Put UART in byte access mode for 16550 compatibility + */ +void soc_uart_set_legacy_mode(void); #endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ |