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Diffstat (limited to 'src/soc/intel/common/block/cse')
-rw-r--r--src/soc/intel/common/block/cse/cse.c1
-rw-r--r--src/soc/intel/common/block/cse/disable_heci.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 648ec6a6f1..b93594aa50 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2017-2018 Intel Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c
index f560a37e9d..3f66a92f38 100644
--- a/src/soc/intel/common/block/cse/disable_heci.c
+++ b/src/soc/intel/common/block/cse/disable_heci.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 Intel Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by