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-rw-r--r--src/soc/intel/cannonlake/bootblock/pch.c2
-rw-r--r--src/soc/intel/cannonlake/pmutil.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 7651cdfe42..8ec4782690 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -56,7 +56,7 @@ static void soc_config_pwrmbase(void)
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */
- setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
+ setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
}
void bootblock_pch_early_init(void)
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 7df8d47fd9..480f65b100 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -246,7 +246,7 @@ void soc_fill_power_state(struct chipset_power_state *ps)
/* STM Support */
uint16_t get_pmbase(void)
{
- return (uint16_t) ACPI_BASE_ADDRESS;
+ return (uint16_t)ACPI_BASE_ADDRESS;
}
/*