diff options
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/graphics.c | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 1db46254c5..cd5e773dbb 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -1,15 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpi.h> -#include <bootmode.h> -#include <console/console.h> #include <fsp/util.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/i915_reg.h> -#include <drivers/intel/gma/libgfxinit.h> -#include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> #include <types.h> @@ -22,8 +16,6 @@ void graphics_soc_init(struct device *dev) { uint32_t ddi_buf_ctl; - intel_gma_init_igd_opregion(); - /* * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. * This will allow the kernel to use 4-lane eDP links properly @@ -35,29 +27,4 @@ void graphics_soc_init(struct device *dev) DDI_BUF_IS_IDLE); graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); } - - /* IGD needs to Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | - PCI_COMMAND_IO); - - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig option and input - * VBT file. - * - * In case of non-FSP solution, SoC need to select another - * Kconfig to perform GFX initialization. - */ - if (CONFIG(RUN_FSP_GOP)) { - /* nothing to do */ - } else if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { - if (!acpi_is_wakeup_s3() && display_init_required()) { - int lightup_ok; - gma_gfxinit(&lightup_ok); - gfx_set_init_done(lightup_ok); - } - } else { - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); - } } |