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Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/chip.c15
-rw-r--r--src/soc/intel/cannonlake/chipset_pch_h.cb4
2 files changed, 16 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index bda66bd1dd..e2e4a6bda5 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -2,6 +2,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ids.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <gpio.h>
@@ -153,10 +154,20 @@ void soc_init_pre_device(void *chip_info)
soc_gpio_pm_configuration();
/* swap enabled PCI ports in device tree if needed */
- if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
+ if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) {
pcie_rp_update_devicetree(pch_h_rp_groups);
- else
+
+ /*
+ * Fix up device ID of hidden PCI device in devicetree.
+ * This is used by soc/intel/common/block/uart.c to generate ACPI
+ */
+ struct device *uart2 = PCH_DEV_UART2;
+ if (uart2->hidden)
+ uart2->device = PCI_DID_INTEL_CNP_H_UART2;
+
+ } else {
pcie_rp_update_devicetree(pch_lp_rp_groups);
+ }
}
static void cpu_fill_ssdt(const struct device *dev)
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index 022e31f67d..77c0d84351 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -92,7 +92,9 @@ chip soc/intel/cannonlake
device pci 17.0 alias sata off end # SATA
device pci 19.0 alias i2c4 off end # I2C #4
device pci 19.1 alias i2c5 off end # I2C #5
- device pci 19.2 alias uart2 off end # UART #2
+ device pci 19.2 alias uart2 off # UART #2
+ ops uart_ops
+ end
device pci 1a.0 alias emmc off end # eMMC
device pci 1b.0 alias pcie_rp17 off end # PCI Express Port 17
device pci 1b.1 alias pcie_rp18 off end # PCI Express Port 18