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-rw-r--r--src/soc/intel/cannonlake/chip.c3
-rw-r--r--src/soc/intel/cannonlake/chip.h6
2 files changed, 2 insertions, 7 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 924764a6c8..30719ed5b1 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -21,6 +21,7 @@
#include <fsp/api.h>
#include <fsp/util.h>
#include <intelblocks/acpi.h>
+#include <intelblocks/chip.h>
#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
@@ -295,7 +296,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Heci3Enabled = config->Heci3Enabled;
params->Device4Enable = config->Device4Enable;
- params->SkipMpInit = !config->use_fsp_mp_init;
+ params->SkipMpInit = !chip_get_fsp_mp_init();
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index a269659f12..4704d1cef6 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -201,12 +201,6 @@ struct soc_intel_cannonlake_config {
uint8_t TcoIrqSelect;
uint8_t TcoIrqEnable;
- /*
- * Option for mainboard to skip coreboot MP initialization
- * 0 = Make use of coreboot MP Init
- * 1 = Make use of FSP MP Init
- */
- uint8_t use_fsp_mp_init;
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
* 3 = GT unsliced, 4 = GT sliced */