diff options
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 5 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 16 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/gspi.c | 16 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/i2c.c | 15 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/soc_chip.h | 21 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/lockdown.c | 24 |
7 files changed, 48 insertions, 50 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f50d9f2bd6..5d8883bc9c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 @@ -188,6 +189,10 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 3 +config SOC_INTEL_I2C_DEV_MAX + int + default 6 + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 47f06aa47d..86f147d0c3 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += gpio.c ramstage-y += i2c.c +ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += nhlt.c diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index d943f9c781..a269659f12 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -18,6 +18,7 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ +#include <intelblocks/chip.h> #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/gspi.h> #include <stdint.h> @@ -30,11 +31,10 @@ #include <soc/usb.h> #include <soc/vr_config.h> -#define CANNONLAKE_I2C_DEV_MAX 6 - struct soc_intel_cannonlake_config { - /* GSPI */ - struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; /* Interrupt Routing configuration. * If bit7 is 1, the interrupt is disabled. */ @@ -201,11 +201,6 @@ struct soc_intel_cannonlake_config { uint8_t TcoIrqSelect; uint8_t TcoIrqEnable; - enum { - CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ - CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ - } chipset_lockdown; - /* * Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init @@ -281,9 +276,6 @@ struct soc_intel_cannonlake_config { /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; - /* I2C bus configuration */ - struct dw_i2c_bus_config i2c[CANNONLAKE_I2C_DEV_MAX]; - /* Enable Pch iSCLK */ uint8_t pch_isclk; diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c index e4f682db42..4b00f3a0f8 100644 --- a/src/soc/intel/cannonlake/gspi.c +++ b/src/soc/intel/cannonlake/gspi.c @@ -16,6 +16,7 @@ #include <assert.h> #include <device/device.h> +#include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <intelblocks/spi.h> #include <soc/iomap.h> @@ -24,19 +25,10 @@ const struct gspi_cfg *gspi_get_soc_cfg(void) { - DEVTREE_CONST struct soc_intel_cannonlake_config *config; - int devfn = SA_DEVFN_ROOT; - DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn); + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - config = dev->chip_info; - - return &config->gspi[0]; + return &common_config->gspi[0]; } uintptr_t gspi_get_soc_early_base(void) diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c index ef3034537f..b53d5a0c1c 100644 --- a/src/soc/intel/cannonlake/i2c.c +++ b/src/soc/intel/cannonlake/i2c.c @@ -18,24 +18,17 @@ #include <device/device.h> #include <device/pci_def.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <intelblocks/chip.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include "chip.h" const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { - const struct soc_intel_cannonlake_config *config; - const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - config = dev->chip_info; - - return &config->i2c[bus]; + return &common_config->i2c[bus]; } uintptr_t dw_i2c_get_soc_early_base(unsigned int bus) diff --git a/src/soc/intel/cannonlake/include/soc/soc_chip.h b/src/soc/intel/cannonlake/include/soc/soc_chip.h new file mode 100644 index 0000000000..3d6f232530 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/soc_chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CANNONLAKE_SOC_CHIP_H_ +#define _SOC_CANNONLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_CANNONLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index 7a3b0c0130..1f1e654636 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <bootstate.h> #include <chip.h> +#include <intelblocks/chip.h> #include <intelblocks/fast_spi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> @@ -27,15 +28,15 @@ #define PCR_DMI_GCS 0x274C #define PCR_DMI_GCS_BILD (1 << 0) -static void pmc_lockdown_cfg(const struct soc_intel_cannonlake_config *config) +static void pmc_lockdown_cfg(const struct soc_intel_common_config *config) { - uint8_t *pmcbase; + uint8_t *pmcbase, reg8; uint32_t reg32, pmsyncreg; /* PMSYNC */ pmcbase = pmc_mmio_regs(); pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); - pmsyncreg |= PMSYNC_LOCK; + pmsyncreg |= PCH2CPU_TPR_CFG_LOCK; write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); /* Lock down ABASE and sleep stretching policy */ @@ -66,7 +67,7 @@ static void dmi_lockdown_cfg(void) pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); } -static void spi_lockdown_cfg(const struct soc_intel_cannonlake_config *config) +static void fast_spi_lockdown_cfg(const struct soc_intel_common_config *config) { /* Set FAST_SPI opcode menu */ fast_spi_set_opcode_menu(); @@ -89,24 +90,17 @@ static void spi_lockdown_cfg(const struct soc_intel_cannonlake_config *config) static void platform_lockdown_config(void *unused) { - struct soc_intel_cannonlake_config *config; - struct device *dev; - - dev = PCH_DEV_SPI; - /* Check if device is valid, else return */ - if (dev == NULL || dev->chip_info == NULL) - return; - - config = dev->chip_info; + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); /* SPI lock down configuration */ - spi_lockdown_cfg(config); + fast_spi_lockdown_cfg(common_config); /* DMI lock down configuration */ dmi_lockdown_cfg(); /* PMC lock down configuration */ - pmc_lockdown_cfg(config); + pmc_lockdown_cfg(common_config); } BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config, |