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-rw-r--r--src/soc/intel/cannonlake/chip.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 51678add67..ef85215623 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -7,6 +7,7 @@
#include <intelblocks/acpi.h>
#include <intelblocks/cfg.h>
#include <intelblocks/itss.h>
+#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
@@ -16,6 +17,19 @@
#include "chip.h"
+static const struct pcie_rp_group pch_lp_rp_groups[] = {
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
+ { 0 }
+};
+
+static const struct pcie_rp_group pch_h_rp_groups[] = {
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
+ { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
+ { 0 }
+};
+
#if CONFIG(HAVE_ACPI_TABLES)
const char *soc_acpi_name(const struct device *dev)
{
@@ -166,6 +180,12 @@ void soc_init_pre_device(void *chip_info)
cnl_configure_pads(NULL, 0);
soc_gpio_pm_configuration();
+
+ /* swap enabled PCI ports in device tree if needed */
+ if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
+ pcie_rp_update_devicetree(pch_h_rp_groups);
+ else
+ pcie_rp_update_devicetree(pch_lp_rp_groups);
}
static struct device_operations pci_domain_ops = {