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-rw-r--r--src/soc/intel/cannonlake/include/soc/pm.h3
-rw-r--r--src/soc/intel/cannonlake/pmutil.c6
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h
index 5b85e74bf5..356f0bcc6f 100644
--- a/src/soc/intel/cannonlake/include/soc/pm.h
+++ b/src/soc/intel/cannonlake/include/soc/pm.h
@@ -172,5 +172,8 @@ void pmc_set_disb(void);
/* Clear PMCON status bits */
void pmc_clear_pmcon_sts(void);
+/* STM Support */
+uint16_t get_pmbase(void);
+
#endif /* !defined(__ACPI__) */
#endif
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index aded9c0cec..2d691adbb2 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -272,3 +272,9 @@ void soc_fill_power_state(struct chipset_power_state *ps)
printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
ps->gblrst_cause[0], ps->gblrst_cause[1]);
}
+
+/* STM Support */
+uint16_t get_pmbase(void)
+{
+ return (uint16_t) ACPI_BASE_ADDRESS;
+}