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-rw-r--r--src/soc/intel/cannonlake/fsp_params.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index f22e39d442..32c5cbb8c6 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -44,6 +44,12 @@ static const struct slot_irq_constraints irq_constraints[] = {
FIXED_INT_PIRQ(SA_DEVFN_PEG0, PCI_INT_A, PIRQ_A),
FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_B, PIRQ_B),
FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_C, PIRQ_C),
+ /*
+ * It looks like FSP does not apply this mapping properly to
+ * the PEG functions. The PINx to PIRQx mapping needs to be there
+ * in ACPI however in case PIN D is used.
+ */
+ FIXED_INT_PIRQ(PCI_DEVFN(SA_DEV_SLOT_PEG, 3), PCI_INT_D, PIRQ_D),
},
},
{