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-rw-r--r--src/soc/intel/cannonlake/acpi.c3
-rw-r--r--src/soc/intel/cannonlake/chip.c3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 9dcaa338c9..0134b86865 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -187,6 +187,9 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ if(config->s0ix_enable)
+ fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
}
uint32_t soc_read_sci_irq_select(void)
{
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index ca2f9a35ec..b2689b0608 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -228,6 +228,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
+ /* S0ix */
+ params->PchPmSlpS0Enable = config->s0ix_enable;
+
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] =