diff options
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/elog.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/xhci.c | 33 |
3 files changed, 36 insertions, 13 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a4a8b71f2..7ff86031cb 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -56,12 +56,14 @@ ramstage-y += systemagent.c ramstage-y += uart.c ramstage-y += vr_config.c ramstage-y += sd.c +ramstage-y += xhci.c smm-y += elog.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += xhci.c postcar-y += memmap.c postcar-y += pmutil.c diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 141aa45b02..0bccdb7880 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -24,18 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pm.h> -#define XHCI_USB2_PORT_STATUS_REG 0x480 -#define XHCI_USB3_PORT_STATUS_REG 0x580 -#define XHCI_USB2_PORT_NUM 14 -#define XHCI_USB3_PORT_NUM 10 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -68,7 +56,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) /* XHCI - "Power Management Event Bus 0" events include XHCI */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - pch_xhci_update_wake_event(&usb_info); + pch_xhci_update_wake_event(soc_get_xhci_usb_info()); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) diff --git a/src/soc/intel/cannonlake/xhci.c b/src/soc/intel/cannonlake/xhci.c new file mode 100644 index 0000000000..2741883d88 --- /dev/null +++ b/src/soc/intel/cannonlake/xhci.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/xhci.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x580 +#define XHCI_USB2_PORT_NUM 14 +#define XHCI_USB3_PORT_NUM 10 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} |