diff options
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/report_platform.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pci_devs.h | 20 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 5 |
5 files changed, 39 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cca783ff21..dcec9bcc8f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -204,6 +204,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX config SOC_INTEL_I2C_DEV_MAX int + default 4 if CANNONLAKE_SOC_PCH_H default 6 # Clock divider parameters for 115200 baud rate diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 937e56cde0..17bcce9822 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -38,6 +38,7 @@ static struct { { CPUID_CANNONLAKE_D0, "Cannonlake D0" }, { CPUID_COFFEELAKE_D0, "Coffeelake D0" }, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"}, + { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, }; static struct { @@ -49,6 +50,8 @@ static struct { { PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)"}, { PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)"}, { PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)"}, + { PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" }, }; static struct { @@ -58,6 +61,8 @@ static struct { { PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" }, { PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" }, { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" }, }; static struct { @@ -74,6 +79,8 @@ static struct { { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" }, { PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2"}, { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1"}, + { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" }, }; static uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0529c5ca8c..4049c1e78c 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -75,6 +75,14 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_PCIE14: return "RP14"; case PCH_DEVFN_PCIE15: return "RP15"; case PCH_DEVFN_PCIE16: return "RP16"; + case PCH_DEVFN_PCIE17: return "RP17"; + case PCH_DEVFN_PCIE18: return "RP18"; + case PCH_DEVFN_PCIE19: return "RP19"; + case PCH_DEVFN_PCIE20: return "RP20"; + case PCH_DEVFN_PCIE21: return "RP21"; + case PCH_DEVFN_PCIE22: return "RP22"; + case PCH_DEVFN_PCIE23: return "RP23"; + case PCH_DEVFN_PCIE24: return "RP24"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; case PCH_DEVFN_GSPI0: return "SPI0"; diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 4d677debe0..63a59db611 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -147,6 +147,24 @@ #define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6) #define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7) +#define PCH_DEV_SLOT_PCIE_2 0x1b +#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0) +#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1) +#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2) +#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3) +#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4) +#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5) +#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6) +#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7) +#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0) +#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1) +#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2) +#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3) +#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4) +#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5) +#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6) +#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7) + #define PCH_DEV_SLOT_SIO3 0x1e #define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) #define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1) diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index b8cddbf542..6b3ccb2a0d 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -31,7 +31,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + if (IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)) + m_cfg->UserBd = BOARD_TYPE_DESKTOP; + else + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->RMT; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { |