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Diffstat (limited to 'src/soc/intel/cannonlake/romstage')
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c3
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c3
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index ce5863855e..c71e4b551a 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -14,7 +14,6 @@
*/
#include <assert.h>
-#include <chip.h>
#include <cpu/x86/msr.h>
#include <console/console.h>
#include <fsp/util.h>
@@ -25,6 +24,8 @@
#include <soc/romstage.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include "../chip.h"
+
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
{
unsigned int i;
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index c168da9a38..661c98a466 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <chip.h>
#include <cpu/x86/mtrr.h>
#include <cbmem.h>
#include <console/console.h>
@@ -30,6 +29,8 @@
#include <string.h>
#include <timestamp.h>
+#include "../chip.h"
+
#define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \
0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \