diff options
Diffstat (limited to 'src/soc/intel/cannonlake/romstage')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5c74d4a1e0..3c5be301b8 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -101,6 +101,28 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) dev = pcidev_path_on_root(SA_DEVFN_IPU); if (dev) m_cfg->SaIpuEnable = dev->enabled; + + /* SATA Gen3 strength */ + for (i = 0; i < SOC_INTEL_CML_SATA_DEV_MAX; i++) { + if (config->sata_port[i].RxGen3EqBoostMagEnable) { + m_cfg->PchSataHsioRxGen3EqBoostMagEnable[i] = + config->sata_port[i].RxGen3EqBoostMagEnable; + m_cfg->PchSataHsioRxGen3EqBoostMag[i] = + config->sata_port[i].RxGen3EqBoostMag; + } + if (config->sata_port[i].TxGen3DownscaleAmpEnable) { + m_cfg->PchSataHsioTxGen3DownscaleAmpEnable[i] = + config->sata_port[i].TxGen3DownscaleAmpEnable; + m_cfg->PchSataHsioTxGen3DownscaleAmp[i] = + config->sata_port[i].TxGen3DownscaleAmp; + } + if (config->sata_port[i].TxGen3DeEmphEnable) { + m_cfg->PchSataHsioTxGen3DeEmphEnable[i] = + config->sata_port[i].TxGen3DeEmphEnable; + m_cfg->PchSataHsioTxGen3DeEmph[i] = + config->sata_port[i].TxGen3DeEmph; + } + } } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |