diff options
Diffstat (limited to 'src/soc/intel/cannonlake/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/romstage.c | 26 |
1 files changed, 1 insertions, 25 deletions
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index b051ad8f92..2604f29576 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -14,10 +14,6 @@ */ #include <arch/io.h> -#include <arch/symbols.h> -#include <assert.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> #include <cbmem.h> #include <console/console.h> #include <fsp/util.h> @@ -29,8 +25,6 @@ asmlinkage void car_stage_entry(void) { bool s3wake; - struct postcar_frame pcf; - uintptr_t top_of_ram; struct chipset_power_state *ps; console_init(); @@ -42,25 +36,7 @@ asmlinkage void car_stage_entry(void) timestamp_add_now(TS_START_ROMSTAGE); s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); - if (postcar_frame_init(&pcf, 1 * KiB)) - die("Unable to initialize postcar frame.\n"); - - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1, - CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - run_postcar_phase(&pcf); + die("Get out from FSP memoryinit. \n"); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |