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path: root/src/soc/intel/cannonlake/romstage/fsp_params.c
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Diffstat (limited to 'src/soc/intel/cannonlake/romstage/fsp_params.c')
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index ac42e0054a..3cd148bc0f 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -52,7 +52,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config)
mask |= (1 << i);
}
m_cfg->PcieRpEnableMask = mask;
- m_cfg->PrmrrSize = get_prmrr_size();
+ m_cfg->PrmrrSize = get_valid_prmrr_size();
m_cfg->EnableC6Dram = config->enable_c6dram;
#if CONFIG(SOC_INTEL_COMETLAKE)
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;