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path: root/src/soc/intel/cannonlake/romstage/fsp_params.c
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Diffstat (limited to 'src/soc/intel/cannonlake/romstage/fsp_params.c')
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index c71e4b551a..6e492bb73a 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -101,6 +101,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
assert(dev != NULL);
const config_t *config = dev->chip_info;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+ FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
soc_memory_init_params(m_cfg, config);
@@ -113,6 +114,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
/* Set debug probe type */
m_cfg->PlatformDebugConsent =
CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT;
+
+ /* Configure VT-d */
+ tconfig->VtdDisable = 0;
+
mainboard_memory_init_params(mupd);
}