diff options
Diffstat (limited to 'src/soc/intel/cannonlake/memmap.c')
| -rw-r--r-- | src/soc/intel/cannonlake/memmap.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 276b9a356d..f0c21d96a5 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -14,9 +14,11 @@ * GNU General Public License for more details. */ +#include <arch/romstage.h> #include <arch/ebda.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> @@ -264,3 +266,18 @@ void *cbmem_top(void) return (void *)(uintptr_t)ebda_cfg.tolum_base; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); +} |