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Diffstat (limited to 'src/soc/intel/cannonlake/include')
-rw-r--r--src/soc/intel/cannonlake/include/soc/pch.h4
-rw-r--r--src/soc/intel/cannonlake/include/soc/pci_devs.h8
2 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h
index d8b3b955b6..7c21dd4b22 100644
--- a/src/soc/intel/cannonlake/include/soc/pch.h
+++ b/src/soc/intel/cannonlake/include/soc/pch.h
@@ -24,6 +24,10 @@
#define PCH_LP 2
#define PCH_UNKNOWN_SERIES 0xFF
+#define PCIE_CLK_NOTUSED 0xFF
+#define PCIE_CLK_LAN 0x70
+#define PCIE_CLK_FREE 0x80
+
u8 pch_revision(void);
u16 pch_type(void);
void pch_log_state(void);
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index ed6b67030b..285fbd68e5 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -134,10 +134,18 @@
#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)
#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)
#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)
+#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4)
+#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5)
+#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6)
+#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7)
#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0)
#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1)
#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2)
#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3)
+#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4)
+#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5)
+#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6)
+#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7)
#define PCH_DEV_SLOT_SIO3 0x1e
#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0)