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path: root/src/soc/intel/cannonlake/fsp_params.c
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Diffstat (limited to 'src/soc/intel/cannonlake/fsp_params.c')
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 8f8c81637c..46d582102f 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -374,8 +374,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */
- params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
- params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
+ params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
+ params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
@@ -448,7 +448,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Set Debug serial port */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
#if !CONFIG(SOC_INTEL_COMETLAKE)
- params->SerialIoEnableDebugUartAfterPost = CONFIG_INTEL_LPSS_UART_FOR_CONSOLE;
+ params->SerialIoEnableDebugUartAfterPost = CONFIG(INTEL_LPSS_UART_FOR_CONSOLE);
#endif
/* Enable CNVi Wifi if enabled in device tree */