diff options
Diffstat (limited to 'src/soc/intel/cannonlake/cpu.c')
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index b6b921a29b..20da942f84 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -27,31 +27,6 @@ static void soc_fsp_load(void) fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -158,9 +133,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - set_aesni_lock(); /* Enable ACPI Timer Emulation via MSR 0x121 */ |