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Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
-rw-r--r--src/soc/intel/cannonlake/chip.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index f84a48015e..3c8a68baf1 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -156,10 +156,10 @@ struct soc_intel_cannonlake_config {
/* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
- uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
+ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC];
/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
* clksrc. */
- uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
+ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC];
/* PCIe LTR(Latency Tolerance Reporting) mechanism */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* Implemented as slot or built-in? */