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Diffstat (limited to 'src/soc/intel/cannonlake/acpi')
-rw-r--r--src/soc/intel/cannonlake/acpi/scs.asl4
-rw-r--r--src/soc/intel/cannonlake/acpi/southbridge.asl2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index 1806e75e87..cdfff911b8 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -112,7 +112,7 @@ Scope (\_SB.PCI0) {
And (PMCR, 0xFFFC, PMCR)
Store (PMCR, ^TEMP)
-#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)
+#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)
/* Change pad mode to Native */
GPMO(SD_PWR_EN_PIN, 0x1)
#endif
@@ -126,7 +126,7 @@ Scope (\_SB.PCI0) {
Or (PMCR, 0x0003, PMCR)
Store (PMCR, ^TEMP)
-#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)
+#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)
/* Change pad mode to GPIO control */
GPMO(SD_PWR_EN_PIN, 0x0)
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index ae8de6a1df..d9ff70b6bc 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -30,7 +30,7 @@
#include "scs.asl"
/* GPIO controller */
-#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
#include "gpio_cnp_h.asl"
#else
#include "gpio.asl"