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Diffstat (limited to 'src/soc/intel/cannonlake/acpi/pci_irqs.asl')
-rw-r--r--src/soc/intel/cannonlake/acpi/pci_irqs.asl202
1 files changed, 122 insertions, 80 deletions
diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl
index eeed667275..d346ce2269 100644
--- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl
+++ b/src/soc/intel/cannonlake/acpi/pci_irqs.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -15,85 +15,127 @@
* GNU General Public License for more details.
*/
-Method(_PRT)
-{
- Return(Package() {
+#include <soc/irq.h>
+
+Name (PICP, Package () {
+ /* PCI Bridge */
+ /* cAVS, SMBus, GbE, Nothpeak */
+ Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ },
+ Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },
+ Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ },
+ Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },
+ /* SerialIo and SCS */
+ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+ Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
+ Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
+ Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
+ /* PCI Express Port 9-16 */
+ Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
+ Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
+ Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
+ Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
+ /* PCI Express Port 1-8 */
+ Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
+ Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
+ Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
+ Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
+ /* eMMC */
+ Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
+ /* SerialIo */
+ Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
+ Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+ Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
+ /* SATA controller */
+ Package(){0x0017FFFF, 0, 0, SATA_IRQ },
+ /* CSME (HECI, IDE-R, Keyboard and Text redirection */
+ Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
+ Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
+ Package(){0x0016FFFF, 2, 0, IDER_IRQ },
+ Package(){0x0016FFFF, 3, 0, KT_IRQ },
+ /* SerialIo */
+ Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+ Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+ Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+ Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
+ /* D20: xHCI, OTG, SRAM, CNVi WiFi */
+ Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
+ Package(){0x0014FFFF, 1, 0, OTG_IRQ },
+ Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
+ Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
+ /* Integrated Sensor Hub */
+ Package(){0x0013FFFF, 0, 0, ISH_IRQ },
+ /* Thermal */
+ Package(){0x0012FFFF, 0, 0, THERMAL_IRQ },
+ /* Host Bridge */
+ /* Root Port D1F0 */
+ Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },
+ Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },
+ Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },
+ Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },
+ /* SA IGFX Device */
+ Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
+ /* SA Thermal Device */
+ Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
+ /* SA IPU Device */
+ Package(){0x0005FFFF, 0, 0, IPU_IRQ },
+ /* SA GNA Device */
+ Package(){0x0008FFFF, 0, 0, GNA_IRQ },
+})
- // PCI Bridge
- // cAVS, SMBus, GbE, Nothpeak
- Package(){0x001FFFFF, 0, 0, 16 },
- Package(){0x001FFFFF, 1, 0, 17 },
- Package(){0x001FFFFF, 2, 0, 18 },
- Package(){0x001FFFFF, 3, 0, 19 },
- // SerialIo and SCS
- Package(){0x001EFFFF, 0, 0, 20 },
- Package(){0x001EFFFF, 1, 0, 21 },
- Package(){0x001EFFFF, 2, 0, 22 },
- Package(){0x001EFFFF, 3, 0, 23 },
- // PCI Express Port 9-16
- Package(){0x001DFFFF, 0, 0, 16 },
- Package(){0x001DFFFF, 1, 0, 17 },
- Package(){0x001DFFFF, 2, 0, 18 },
- Package(){0x001DFFFF, 3, 0, 19 },
- // PCI Express Port 1-8
- Package(){0x001CFFFF, 0, 0, 16 },
- Package(){0x001CFFFF, 1, 0, 17 },
- Package(){0x001CFFFF, 2, 0, 18 },
- Package(){0x001CFFFF, 3, 0, 19 },
- // PCI Express Port 17-20
- Package(){0x001BFFFF, 0, 0, 16 },
- Package(){0x001BFFFF, 1, 0, 17 },
- Package(){0x001BFFFF, 2, 0, 18 },
- Package(){0x001BFFFF, 3, 0, 19 },
- // eMMC
- Package(){0x001AFFFF, 0, 0, 16 },
- Package(){0x001AFFFF, 1, 0, 17 },
- Package(){0x001AFFFF, 2, 0, 18 },
- Package(){0x001AFFFF, 3, 0, 19 },
- // SerialIo
- Package(){0x0019FFFF, 0, 0, 32 },
- Package(){0x0019FFFF, 1, 0, 33 },
- Package(){0x0019FFFF, 2, 0, 34 },
- // SATA controller
- Package(){0x0017FFFF, 0, 0, 16 },
- // CSME (HECI, IDE-R, Keyboard and Text redirection
- Package(){0x0016FFFF, 0, 0, 16 },
- Package(){0x0016FFFF, 1, 0, 17 },
- Package(){0x0016FFFF, 2, 0, 18 },
- Package(){0x0016FFFF, 3, 0, 19 },
- // SerialIo
- Package(){0x0015FFFF, 0, 0, 16 },
- Package(){0x0015FFFF, 1, 0, 17 },
- Package(){0x0015FFFF, 2, 0, 18 },
- Package(){0x0015FFFF, 3, 0, 19 },
- // CNL: D20: xHCI, OTG, CNVi WiFi, SDcard
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
- // Integrated Sensor Hub
- Package(){0x0013FFFF, 0, 0, 20 },
- // Thermal, UFS, SerialIo SPI 2
- Package(){0x0012FFFF, 0, 0, 16 },
- Package(){0x0012FFFF, 1, 0, 24 },
- Package(){0x0012FFFF, 2, 0, 18 },
- Package(){0x0012FFFF, 3, 0, 19 },
+Name (PICN, Package () {
+ /* D31: cAVS, SMBus, GbE, Nothpeak */
+ Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },
+ Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },
+ Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },
+ Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },
+ /* D32: Can't use PIC*/
+ /* D29: PCI Express Port 9-16 */
+ Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },
+ Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },
+ Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },
+ Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },
+ /* D28: PCI Express Port 1-8 */
+ Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },
+ Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },
+ Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },
+ Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },
+ /* D25: Can't use PIC*/
+ /* D23 */
+ Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ /* D22: CSME (HECI, IDE-R, KT redirection */
+ Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },
+ Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },
+ Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },
+ /* D21: Can't use PIC*/
+ /* D20: xHCI, OTG, SRAM, CNVi WiFi */
+ Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },
+ Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },
+ Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },
+ /* D19: Can't use PIC*/
+ /* Thermal */
+ Package () { 0x0012FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ /* P.E.G. Root Port D1F0 */
+ Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },
+ Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },
+ Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },
+ /* SA IGFX Device */
+ Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ /* SA Thermal Device */
+ Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ /* SA IPU Device */
+ Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ /* SA GNA Device */
+ Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },
+})
- // Host Bridge
- // Root Port D1F0
- Package(){0x0001FFFF, 0, 0, 16 },
- Package(){0x0001FFFF, 1, 0, 17 },
- Package(){0x0001FFFF, 2, 0, 18 },
- Package(){0x0001FFFF, 3, 0, 19 },
- // Root Port D1F1
- // Root Port D1F2
- // IGFX Device
- Package(){0x0002FFFF, 0, 0, 16 },
- // Thermal Device
- Package(){0x0004FFFF, 0, 0, 16 },
- // IPU Device
- Package(){0x0005FFFF, 0, 0, 16 },
- // GNA Device
- Package(){0x0008FFFF, 0, 0, 16 },
- })
+Method (_PRT)
+{
+ If (PICM) {
+ Return (^PICP)
+ } Else {
+ Return (^PICN)
+ }
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-06 02:54:43 +0000