aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/broadwell/systemagent.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/broadwell/systemagent.c')
-rw-r--r--src/soc/intel/broadwell/systemagent.c20
1 files changed, 17 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index f46f5eac35..d9dbfe93c6 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -271,7 +271,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values)
printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
}
-static void mc_add_dram_resources(device_t dev)
+static void mc_add_dram_resources(device_t dev, int *resource_cnt)
{
unsigned long base_k, size_k;
unsigned long touud_k;
@@ -327,7 +327,7 @@ static void mc_add_dram_resources(device_t dev)
* The resource index starts low and should not meet or exceed
* PCI_BASE_ADDRESS_0.
*/
- index = 0;
+ index = *resource_cnt;
/* 0 - > 0xa0000 */
base_k = 0;
@@ -373,18 +373,32 @@ static void mc_add_dram_resources(device_t dev)
(0x100000 - 0xc0000) >> 10);
chromeos_reserve_ram_oops(dev, index++);
+
+ *resource_cnt = index;
}
static void systemagent_read_resources(device_t dev)
{
+ int index = 0;
+ const bool vtd_capable =
+ !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
+
/* Read standard PCI resources. */
pci_dev_read_resources(dev);
/* Add all fixed MMIO resources. */
mc_add_fixed_mmio_resources(dev);
+ /* Add VT-d MMIO resources if capable */
+ if (vtd_capable) {
+ mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB,
+ GFXVT_BASE_SIZE / KiB);
+ mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB,
+ VTVC0_BASE_SIZE / KiB);
+ }
+
/* Calculate and add DRAM resources. */
- mc_add_dram_resources(dev);
+ mc_add_dram_resources(dev, &index);
}
static void systemagent_init(struct device *dev)