diff options
Diffstat (limited to 'src/soc/intel/broadwell/romstage')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/power_state.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/raminit.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 291d5eb9ea..ca22b4ef5b 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -57,7 +57,7 @@ static int prev_sleep_state(struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index acb435bce0..04657aebd8 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -24,7 +24,7 @@ #include <memory_info.h> #include <mrc_cache.h> #include <string.h> -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #endif @@ -57,7 +57,7 @@ void raminit(struct pei_data *pei_data) pei_data->saved_data_size = region_device_sz(&rdev); pei_data->saved_data = rdev_mmap_full(&rdev); /* Assume boot device is memory mapped. */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); } else if (pei_data->boot_mode == ACPI_S3) { /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); @@ -104,7 +104,7 @@ void raminit(struct pei_data *pei_data) if (pei_data->boot_mode != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 9aa31b85c1..2531665f1f 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -123,7 +123,7 @@ void romstage_common(struct romstage_params *params) params->pei_data->boot_mode = params->power_state->prev_sleep_state; -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) if (params->power_state->prev_sleep_state != ACPI_S3) boot_count_increment(); #endif |