diff options
Diffstat (limited to 'src/soc/intel/broadwell/romstage')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/stack.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 37d7f30a68..24720d14a3 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -147,7 +147,7 @@ clear_mtrrs: wrmsr post_code(0x27) - /* Enable caching for ram init code to run faster */ + /* Enable caching for RAM init code to run faster */ movl $MTRR_PHYS_BASE(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c index 76307cfbb5..86a1c02b15 100644 --- a/src/soc/intel/broadwell/romstage/stack.c +++ b/src/soc/intel/broadwell/romstage/stack.c @@ -78,7 +78,7 @@ void *setup_stack_and_mttrs(void) num_mtrrs++; top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the + /* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the * start of the TSEG region. It is required to be 8MiB aligned. Set * this area as cacheable so it can be used later for ramstage before * setting up the entire RAM as cacheable. */ @@ -88,7 +88,7 @@ void *setup_stack_and_mttrs(void) slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); num_mtrrs++; - /* Cache 8MiB at the top of ram. Top of ram is where the TSEG + /* Cache 8MiB at the top of ram. Top of RAM is where the TSEG * region resides. However, it is not restricted to SMM mode until * SMM has been relocated. By setting the region to cacheable it * provides faster access when relocating the SMM handler as well |