diff options
Diffstat (limited to 'src/soc/intel/broadwell/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 35 |
1 files changed, 34 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 7a796f4a69..1e925212b4 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -19,6 +19,7 @@ #include <arch/cbfs.h> #include <arch/early_variables.h> #include <bootmode.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <elog.h> @@ -32,6 +33,36 @@ #include <soc/romstage.h> #include <soc/spi.h> +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +static void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); +} + /* Entry from cache-as-ram.inc. */ asmlinkage void *romstage_main(unsigned long bist, uint32_t tsc_low, uint32_t tsc_hi) @@ -74,7 +105,9 @@ asmlinkage void *romstage_main(unsigned long bist, /* Call into mainboard. */ mainboard_romstage_entry(&rp); - return setup_stack_and_mtrrs(); + platform_enter_postcar(); + + return NULL; } /* Entry from the mainboard. */ |