1 files changed, 0 insertions, 41 deletions
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index ecdadb7f9b..ef97a1e3fa 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -27,46 +27,6 @@
 #include <soc/smbus.h>
 #include <soc/intel/broadwell/chip.h>
 
-const struct reg_script pch_early_init_script[] = {
-	/* Setup southbridge BARs */
-	REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1),
-	REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1),
-	REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),
-	REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),
-	REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),
-
-	/* Set COM1/COM2 decode range */
-	REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),
-	/* Enable legacy decode ranges */
-	REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
-			COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),
-
-	/* Enable IOAPIC */
-	REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),
-	/* Read back for posted write */
-	REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),
-
-	/* Set HPET address and enable it */
-	REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),
-	/* Read back for posted write */
-	REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),
-	/* Enable HPET to start counter */
-	REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),
-
-	/* Disable reset */
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)),
-	/* TCO timer halt */
-	REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),
-
-	/* Enable upper 128 bytes of CMOS */
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)),
-
-	/* Disable unused device (always) */
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS),
-
-	REG_SCRIPT_END
-};
-
 const struct reg_script pch_interrupt_init_script[] = {
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
@@ -132,7 +92,6 @@ static void pch_enable_lpc(void)
 
 void pch_early_init(void)
 {
-	reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);
 	reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script);
 
 	pch_enable_lpc();