diff options
Diffstat (limited to 'src/soc/intel/broadwell/pch')
| -rw-r--r-- | src/soc/intel/broadwell/pch/acpi/globalnvs.asl | 36 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pch/adsp.c | 17 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pch/serialio.c | 15 |
3 files changed, 12 insertions, 56 deletions
diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index b83b957c6c..88fe4b1218 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -12,7 +12,7 @@ Name (\PICM, 0) // IOAPIC/8259 */ External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -47,40 +47,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> - - Offset (0x1000), - /* Device enables in ACPI mode */ - S0EN, 8, // DMA Enable - S1EN, 8, // I2C0 Enable - S2EN, 8, // I2C1 Enable - S3EN, 8, // SPI0 Enable - S4EN, 8, // SPI1 Enable - S5EN, 8, // UART0 Enable - S6EN, 8, // UART1 Enable - S7EN, 8, // SDIO Enable - S8EN, 8, // ADSP Enable - - /* BAR 0 */ - S0B0, 32, // DMA BAR0 - S1B0, 32, // I2C0 BAR0 - S2B0, 32, // I2C1 BAR0 - S3B0, 32, // SPI0 BAR0 - S4B0, 32, // SPI1 BAR0 - S5B0, 32, // UART0 BAR0 - S6B0, 32, // UART1 BAR0 - S7B0, 32, // SDIO BAR0 - S8B0, 32, // ADSP BAR0 - - /* BAR 1 */ - S0B1, 32, // DMA BAR1 - S1B1, 32, // I2C0 BAR1 - S2B1, 32, // I2C1 BAR1 - S3B1, 32, // SPI0 BAR1 - S4B1, 32, // SPI1 BAR1 - S5B1, 32, // UART0 BAR1 - S6B1, 32, // UART1 BAR1 - S7B1, 32, // SDIO BAR1 - S8B1, 32, // ADSP BAR1 } /* Set flag to enable USB charging in S3 */ diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/soc/intel/broadwell/pch/adsp.c index 06dd38bd8a..a65ff4b469 100644 --- a/src/soc/intel/broadwell/pch/adsp.c +++ b/src/soc/intel/broadwell/pch/adsp.c @@ -10,7 +10,7 @@ #include <soc/adsp.h> #include <soc/device_nvs.h> #include <soc/iobp.h> -#include <soc/nvs.h> +#include <soc/device_nvs.h> #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/rcba.h> @@ -79,20 +79,15 @@ static void adsp_init(struct device *dev) pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE); if (config->sio_acpi_mode) { - /* Configure for ACPI mode */ - struct global_nvs *gnvs; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + /* Configure for ACPI mode */ printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n"); - /* Find ACPI NVS to update BARs */ - gnvs = acpi_get_gnvs(); - if (!gnvs) - return; - /* Save BAR0 and BAR1 to ACPI NVS */ - gnvs->dev.bar0[SIO_NVS_ADSP] = (u32)bar0->base; - gnvs->dev.bar1[SIO_NVS_ADSP] = (u32)bar1->base; - gnvs->dev.enable[SIO_NVS_ADSP] = 1; + dev_nvs->bar0[SIO_NVS_ADSP] = (u32)bar0->base; + dev_nvs->bar1[SIO_NVS_ADSP] = (u32)bar1->base; + dev_nvs->enable[SIO_NVS_ADSP] = 1; /* Set PCI Config Disable Bit */ pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD); diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/soc/intel/broadwell/pch/serialio.c index d32a27ddca..28f34b7d53 100644 --- a/src/soc/intel/broadwell/pch/serialio.c +++ b/src/soc/intel/broadwell/pch/serialio.c @@ -8,7 +8,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <soc/iobp.h> -#include <soc/nvs.h> +#include <soc/device_nvs.h> #include <soc/pci_devs.h> #include <soc/pch.h> #include <soc/ramstage.h> @@ -233,20 +233,15 @@ static void serialio_init(struct device *dev) } if (config->sio_acpi_mode) { - struct global_nvs *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = acpi_get_gnvs(); - if (!gnvs) - return; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); /* Save BAR0 and BAR1 to ACPI NVS */ - gnvs->dev.bar0[sio_index] = (u32)bar0->base; - gnvs->dev.bar1[sio_index] = (u32)bar1->base; + dev_nvs->bar0[sio_index] = (u32)bar0->base; + dev_nvs->bar1[sio_index] = (u32)bar1->base; /* Do not enable UART if it is used as debug port */ if (!serialio_uart_is_debug(dev)) - gnvs->dev.enable[sio_index] = 1; + dev_nvs->enable[sio_index] = 1; /* Put device in D3hot state via BAR1 */ if (dev->path.pci.devfn != PCH_DEVFN_SDMA) |