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-rw-r--r--src/soc/intel/broadwell/include/soc/nvs.h3
-rw-r--r--src/soc/intel/broadwell/include/soc/pm.h2
2 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 41b2e4a8ba..195dd43c3e 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -53,7 +53,8 @@ typedef struct {
u32 obsolete_cmem; /* 0x19 - 0x1c - CBMEM TOC */
u32 cbmc; /* 0x1d - 0x20 - Coreboot Memory Console */
u32 pm1i; /* 0x21 - 0x24 - PM1 wake status bit */
- u8 rsvd3[219];
+ u32 gpei; /* 0x25 - 0x28 - GPE wake status bit */
+ u8 rsvd3[215];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h
index 6bc98ef339..54fc4a7f1d 100644
--- a/src/soc/intel/broadwell/include/soc/pm.h
+++ b/src/soc/intel/broadwell/include/soc/pm.h
@@ -83,6 +83,8 @@
#define TCO2_STS 0x66
#define TCO2_STS_SECOND_TO (1 << 1)
+#define GPE0_REG_MAX 4
+#define GPE0_REG_SIZE 32
#define GPE0_STS(x) (0x80 + (x * 4))
#define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */
#define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */