aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/broadwell/igd.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/broadwell/igd.c')
-rw-r--r--src/soc/intel/broadwell/igd.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 8235b3f3df..eac9ac1ec1 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -472,6 +472,7 @@ static void igd_init(struct device *dev)
{
int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
u32 rp1_gfx_freq;
+ extern int oprom_is_loaded;
/* IGD needs to be Bus Master */
u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
@@ -510,6 +511,18 @@ static void igd_init(struct device *dev)
igd_cdclk_init_haswell(dev);
reg_script_run_on_dev(dev, haswell_late_init_script);
}
+
+ if (!oprom_is_loaded) {
+ /*
+ * Enable DDI-A if the Option ROM did not execute:
+ *
+ * bit 0: Display detected (RO)
+ * bit 4: DDI A supports 4 lanes and DDI E is not used
+ * bit 7: DDI buffer is idle
+ */
+ gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES |
+ DDI_INIT_DISPLAY_DETECTED);
+ }
}
static void igd_read_resources(struct device *dev)