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-rw-r--r--src/soc/intel/braswell/gfx.c2
-rw-r--r--src/soc/intel/braswell/lpss.c3
2 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c
index 1bd0033313..7599329b61 100644
--- a/src/soc/intel/braswell/gfx.c
+++ b/src/soc/intel/braswell/gfx.c
@@ -14,7 +14,7 @@
static const struct reg_script gpu_pre_vbios_script[] = {
/* Make sure GFX is bus master with MMIO access */
- REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
+ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY),
REG_SCRIPT_END
};
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index 7ff42c35df..961d405156 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -19,7 +19,8 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
- REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
+ REG_PCI_OR16(PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),