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-rw-r--r--src/soc/intel/baytrail/baytrail/msr.h1
-rw-r--r--src/soc/intel/baytrail/tsc_freq.c21
2 files changed, 19 insertions, 3 deletions
diff --git a/src/soc/intel/baytrail/baytrail/msr.h b/src/soc/intel/baytrail/baytrail/msr.h
index 7f3b3b26fd..5094f965c7 100644
--- a/src/soc/intel/baytrail/baytrail/msr.h
+++ b/src/soc/intel/baytrail/baytrail/msr.h
@@ -21,6 +21,7 @@
#define _BAYTRAIL_MSR_H_
#define MSR_IA32_PLATFORM_ID 0x17
+#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd
#define MSR_PLATFORM_INFO 0xce
#define MSR_IA32_PERF_CTL 0x199
#define MSR_IA32_MISC_ENABLES 0x1a0
diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c
index 0cf7273b74..e4327318da 100644
--- a/src/soc/intel/baytrail/tsc_freq.c
+++ b/src/soc/intel/baytrail/tsc_freq.c
@@ -27,14 +27,29 @@
#include <baytrail/romstage.h>
#endif
-
-#define BCLK 100 /* 100 MHz */
unsigned long tsc_freq_mhz(void)
{
msr_t platform_info;
+ msr_t clk_info;
+ unsigned long bclk_khz;
platform_info = rdmsr(MSR_PLATFORM_INFO);
- return BCLK * ((platform_info.lo >> 8) & 0xff);
+ clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
+ switch (clk_info.lo & 0x3) {
+ case 0:
+ bclk_khz = 83333;
+ break;
+ case 1:
+ bclk_khz = 100000;
+ break;
+ case 2:
+ bclk_khz = 133333;
+ break;
+ case 3:
+ bclk_khz = 116666;
+ break;
+ }
+ return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
}
void set_max_freq(void)