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-rw-r--r--src/soc/intel/baytrail/acpi/device_nvs.asl3
-rw-r--r--src/soc/intel/baytrail/acpi/globalnvs.asl10
2 files changed, 0 insertions, 13 deletions
diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl
index aa0e9533f8..d570788985 100644
--- a/src/soc/intel/baytrail/acpi/device_nvs.asl
+++ b/src/soc/intel/baytrail/acpi/device_nvs.asl
@@ -1,8 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-External (NVSD)
-
-OperationRegion (DNVS, SystemMemory, NVSD, 0x1000)
Field (DNVS, ByteAcc, NoLock, Preserve)
{
/* Device Enabled in ACPI Mode */
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index 293daa94a3..eb51cada51 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -4,16 +4,6 @@
Name(\PICM, 0) /* IOAPIC/8259 */
-/*
- * Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External (NVSA)
-
-OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */