diff options
Diffstat (limited to 'src/soc/intel/baytrail')
-rw-r--r-- | src/soc/intel/baytrail/cpu.c | 2 | ||||
-rw-r--r-- | src/soc/intel/baytrail/include/soc/msr.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 618430b9a8..9bbeafbe76 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -35,7 +35,7 @@ /* Core level MSRs */ const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), + REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), /* Disable C1E */ diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index 689d4d55cc..b332478734 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -19,7 +19,7 @@ #define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) |