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Diffstat (limited to 'src/soc/intel/baytrail/lpe.c')
-rw-r--r--src/soc/intel/baytrail/lpe.c104
1 files changed, 85 insertions, 19 deletions
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 24daf5575d..581f42bfa9 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -18,12 +18,18 @@
*/
#include <arch/io.h>
+#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <reg_script.h>
#include <baytrail/iomap.h>
+#include <baytrail/iosf.h>
+#include <baytrail/lpc.h>
+#include <baytrail/nvs.h>
+#include <baytrail/pattrs.h>
#include <baytrail/pci_devs.h>
#include <baytrail/pmc.h>
#include <baytrail/ramstage.h>
@@ -34,8 +40,52 @@
* address. Just take 1MiB @ 512MiB. */
#define FIRMWARE_PHYS_BASE (512 << 20)
#define FIRMWARE_PHYS_LENGTH (1 << 20)
-#define FIRMWARE_REG_BASE 0xa8
-#define FIRMWARE_REG_LENGTH 0xac
+#define FIRMWARE_PCI_REG_BASE 0xa8
+#define FIRMWARE_PCI_REG_LENGTH 0xac
+#define FIRMWARE_REG_BASE_C0 0x144000
+#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
+
+static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
+{
+ struct resource *res;
+
+ res = find_resource(dev, index);
+ if (res)
+ *field = res->base;
+}
+
+static void lpe_enable_acpi_mode(device_t dev)
+{
+ static const struct reg_script ops[] = {
+ /* Disable PCI interrupt, enable Memory and Bus Master */
+ REG_PCI_OR32(PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
+ /* Enable ACPI mode */
+ REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1,
+ LPE_PCICFGCTR1_PCI_CFG_DIS |
+ LPE_PCICFGCTR1_ACPI_INT_EN),
+ REG_SCRIPT_END
+ };
+ global_nvs_t *gnvs;
+
+ /* Find ACPI NVS to update BARs */
+ gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS);
+ if (!gnvs) {
+ printk(BIOS_ERR, "Unable to locate Global NVS\n");
+ return;
+ }
+
+ /* Save BAR0, BAR1, and firmware base to ACPI NVS */
+ assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
+ assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1);
+ assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
+
+ /* Device is enabled in ACPI mode */
+ gnvs->dev.lpe_en = 1;
+
+ /* Put device in ACPI mode */
+ reg_script_run_on_dev(dev, ops);
+}
static void setup_codec_clock(device_t dev)
{
@@ -75,38 +125,54 @@ static void setup_codec_clock(device_t dev)
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
}
+static void lpe_stash_firmware_info(device_t dev)
+{
+ struct resource *res;
+ struct resource *mmio;
+ const struct pattrs *pattrs = pattrs_get();
+
+ res = find_resource(dev, FIRMWARE_PCI_REG_BASE);
+ if (res == NULL) {
+ printk(BIOS_DEBUG, "LPE Firmware memory not found.\n");
+ return;
+ }
+
+ /* Continue using old way of informing firmware address / size. */
+ pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base);
+ pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size);
+
+ /* C0 and later steppings use an offset in the MMIO space. */
+ if (pattrs->stepping >= STEP_C0) {
+ mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
+ write32(mmio->base + FIRMWARE_REG_BASE_C0, res->base);
+ write32(mmio->base + FIRMWARE_REG_LENGTH_C0, res->size);
+ }
+}
+
static void lpe_init(device_t dev)
{
+ struct soc_intel_baytrail_config *config = dev->chip_info;
+
+ lpe_stash_firmware_info(dev);
+
setup_codec_clock(dev);
+
+ if (config->lpe_acpi_mode)
+ lpe_enable_acpi_mode(dev);
}
static void lpe_read_resources(device_t dev)
{
pci_dev_read_resources(dev);
- reserved_ram_resource(dev, FIRMWARE_REG_BASE,
+ reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE,
FIRMWARE_PHYS_BASE >> 10,
FIRMWARE_PHYS_LENGTH >> 10);
}
-static void lpe_set_resources(device_t dev)
-{
- struct resource *res;
-
- pci_dev_set_resources(dev);
-
- res = find_resource(dev, FIRMWARE_REG_BASE);
- if (res == NULL) {
- printk(BIOS_DEBUG, "LPE Firmware memory not found.\n");
- return;
- }
- pci_write_config32(dev, FIRMWARE_REG_BASE, res->base);
- pci_write_config32(dev, FIRMWARE_REG_LENGTH, res->size);
-}
-
static const struct device_operations device_ops = {
.read_resources = lpe_read_resources,
- .set_resources = lpe_set_resources,
+ .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = lpe_init,
.enable = NULL,