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-rw-r--r--src/soc/intel/baytrail/acpi/dptf/charger.asl36
-rw-r--r--src/soc/intel/baytrail/acpi/dptf/cpu.asl180
-rw-r--r--src/soc/intel/baytrail/acpi/dptf/dptf.asl51
-rw-r--r--src/soc/intel/baytrail/acpi/dptf/thermal.asl116
-rw-r--r--src/soc/intel/baytrail/acpi/globalnvs.asl5
5 files changed, 388 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/acpi/dptf/charger.asl b/src/soc/intel/baytrail/acpi/dptf/charger.asl
new file mode 100644
index 0000000000..7560f139be
--- /dev/null
+++ b/src/soc/intel/baytrail/acpi/dptf/charger.asl
@@ -0,0 +1,36 @@
+Device (TCHG)
+{
+ Name (_HID, "INT3403")
+ Name (_UID, 0)
+ Name (PTYP, 0x0B)
+ Name (_STR, Unicode("Battery Charger"))
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Name (PPSS, Package ()
+ {
+ Package () { 0, 0, 0, 0, 0, 0x880, "mA", 0 }, /* 2.1A */
+ Package () { 0, 0, 0, 0, 1, 0x800, "mA", 0 }, /* 2.0A */
+ Package () { 0, 0, 0, 0, 2, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 3, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 4, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 5, 0x000, "mA", 0 }, /* 0.0A */
+ })
+
+ Method (PPPC)
+ {
+ Return (0)
+ }
+
+ Method (SPPC, 1, Serialized)
+ {
+ /* TODO: Tell EC to limit battery charging */
+ }
+}
diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl
new file mode 100644
index 0000000000..6e6c7921a0
--- /dev/null
+++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl
@@ -0,0 +1,180 @@
+External (\_PR.CPU0._TSS, MethodObj)
+External (\_PR.CPU0._TPC, MethodObj)
+External (\_PR.CPU0._PTC, PkgObj)
+External (\_PR.CPU0._TSD, PkgObj)
+External (\_PR.CPU0._PPC, MethodObj)
+External (\_PR.CPU0._PSS, MethodObj)
+
+Device (TCPU)
+{
+ Name (_HID, EISAID ("INT3401"))
+ Name (_UID, 0)
+ Name (CTYP, 0) /* Passive Cooling by default */
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /*
+ * Processor Throttling Controls
+ */
+
+ Method (_TSS)
+ {
+ If (CondRefOf (\_PR.CPU0._TSS)) {
+ Return (\_PR.CPU0._TSS)
+ } Else {
+ Return (Package ()
+ {
+ Package () { 0, 0, 0, 0, 0 }
+ })
+ }
+ }
+
+ Method (_TPC)
+ {
+ If (CondRefOf (\_PR.CPU0._TPC)) {
+ Return (\_PR.CPU0._TPC)
+ } Else {
+ Return (0)
+ }
+ }
+
+ Method (_PTC)
+ {
+ If (CondRefOf (\_PR.CPU0._PTC)) {
+ Return (\_PR.CPU0._PTC)
+ } Else {
+ Return (Package ()
+ {
+ Buffer () { 0 },
+ Buffer () { 0 }
+ })
+ }
+ }
+
+ Method (_TSD)
+ {
+ If (CondRefOf (\_PR.CPU0._TSD)) {
+ Return (\_PR.CPU0._TSD)
+ } Else {
+ Return (Package ()
+ {
+ Package () { 5, 0, 0, 0, 0 }
+ })
+ }
+ }
+
+ Method (_TDL)
+ {
+ If (CondRefOf (\_PR.CPU0._TSS)) {
+ Store (SizeOf (\_PR.CPU0._TSS ()), Local0)
+ Decrement (Local0)
+ Return (Local0)
+ } Else {
+ Return (0)
+ }
+ }
+
+ /*
+ * Processor Performance Control
+ */
+
+ Method (_PPC)
+ {
+ If (CondRefOf (\_PR.CPU0._PPC)) {
+ Return (\_PR.CPU0._PPC)
+ } Else {
+ Return (0)
+ }
+ }
+
+ Method (SPPC, 1)
+ {
+ Store (Arg0, \PPCM)
+
+ /* Notify OS to re-read _PPC limit on each CPU */
+ \PPCN ()
+ }
+
+ Method (_PSS)
+ {
+ If (CondRefOf (\_PR.CPU0._PSS)) {
+ Return (\_PR.CPU0._PSS)
+ } Else {
+ Return (Package ()
+ {
+ Package () { 0, 0, 0, 0, 0, 0 }
+ })
+ }
+ }
+
+ Method (_PDL)
+ {
+ If (CondRefOf (\_PR.CPU0._PSS)) {
+ Store (SizeOf (\_PR.CPU0._PSS ()), Local0)
+ Decrement (Local0)
+ Return (Local0)
+ } Else {
+ Return (0)
+ }
+ }
+
+ /*
+ * DPTF
+ */
+
+ /* Convert from Degrees C to 1/10 Kelvin for ACPI */
+ Method (CTOK, 1) {
+ /* 10th of Degrees C */
+ Multiply (Arg0, 10, Local0)
+
+ /* Convert to Kelvin */
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ /* Critical temperature from NVS */
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ /* Hot temperature is 3 less than critical temperature */
+ Method (_HOT, 0, Serialized)
+ {
+ Return (CTOK (Subtract (\TCRT, 3)))
+ }
+
+ Method (_PSV, 0, Serialized)
+ {
+ If (CTYP) {
+ Return (CTOK (\TACT))
+ } Else {
+ Return (CTOK (\TPSV))
+ }
+ }
+
+ /* Set Cooling Policy
+ * Arg0 - Cooling policy mode, 1=active, 0=passive
+ * Arg1 - Acoustic Limit
+ * Arg2 - Power Limit
+ */
+ Method (_SCP, 3, Serialized)
+ {
+ If (LEqual (Arg0, 0)) {
+ Store (0, CTYP)
+ } Else {
+ Store (1, CTYP)
+ }
+
+ /* DPTF Thermal Trip Points Changed Event */
+ Notify (TCPU, 0x91)
+ }
+}
diff --git a/src/soc/intel/baytrail/acpi/dptf/dptf.asl b/src/soc/intel/baytrail/acpi/dptf/dptf.asl
new file mode 100644
index 0000000000..b6368868e3
--- /dev/null
+++ b/src/soc/intel/baytrail/acpi/dptf/dptf.asl
@@ -0,0 +1,51 @@
+Device (DPTF)
+{
+ Name (_HID, EISAID ("INT3400"))
+ Name (_UID, 0)
+
+ Name (IDSP, Package()
+ {
+ /* DPPM Passive Policy 1.0 */
+ ToUUID("42A441D6-AE6A-462B-A84B-4A8CE79027D3"),
+
+ /* DPPM Critical Policy */
+ ToUUID("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"),
+
+ /* DPPM Cooling Policy */
+ ToUUID("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"),
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Method (_OSC, 4, Serialized)
+ {
+ /* TODO: Enable/Disable EC control of thermals/charging */
+ Return (Arg3)
+ }
+
+ Method (_TRT)
+ {
+ Return (\_SB.DTRT)
+ }
+
+ /* Thermal Threshold Event Handler */
+ Method (TEVT, 0, Serialized)
+ {
+ }
+
+ /* Include CPU Participant */
+ #include "cpu.asl"
+
+ /* Include Thermal Participants */
+ #include "thermal.asl"
+
+ /* Include Charger Participant */
+ #include "charger.asl"
+}
diff --git a/src/soc/intel/baytrail/acpi/dptf/thermal.asl b/src/soc/intel/baytrail/acpi/dptf/thermal.asl
new file mode 100644
index 0000000000..2a77e6ae0b
--- /dev/null
+++ b/src/soc/intel/baytrail/acpi/dptf/thermal.asl
@@ -0,0 +1,116 @@
+#ifdef DPTF_TSR0_SENSOR_ID
+Device (TSR0)
+{
+ Name (_HID, EISAID ("INT3403"))
+ Name (_UID, 1)
+ Name (PTYP, 0x03)
+ Name (TMPI, DPTF_TSR0_SENSOR_ID)
+ Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME))
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+ }
+
+ Name (PATC, 2)
+
+ /* Set Aux Trip Point */
+ Method (PAT0, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+ }
+
+ /* Set Aux Trip Point */
+ Method (PAT1, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+ }
+}
+#endif
+
+#ifdef DPTF_TSR1_SENSOR_ID
+Device (TSR1)
+{
+ Name (_HID, EISAID ("INT3403"))
+ Name (_UID, 2)
+ Name (PTYP, 0x03)
+ Name (TMPI, DPTF_TSR1_SENSOR_ID)
+ Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME))
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+ }
+
+ Name (PATC, 2)
+
+ /* Set Aux Trip Point */
+ Method (PAT0, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+ }
+
+ /* Set Aux Trip Point */
+ Method (PAT1, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+ }
+}
+#endif
+
+#ifdef DPTF_TSR2_SENSOR_ID
+Device (TSR2)
+{
+ Name (_HID, EISAID ("INT3403"))
+ Name (_UID, 3)
+ Name (PTYP, 0x03)
+ Name (TMPI, DPTF_TSR2_SENSOR_ID)
+ Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME))
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+ }
+
+ Name (PATC, 2)
+
+ /* Set Aux Trip Point */
+ Method (PAT0, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+ }
+
+ /* Set Aux Trip Point */
+ Method (PAT1, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+ }
+}
+#endif
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index 2f614a9806..cd008243ca 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -51,6 +51,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PCNT, 8, // 0x11 - Processor count
TPMP, 8, // 0x12 - TPM Present and Enabled
TLVL, 8, // 0x13 - Throttle Level
+ PPCM, 8, // 0x14 - Maximum P-state usable by OS
/* Device Config */
Offset (0x20),
@@ -58,6 +59,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
S5U1, 8, // 0x21 - Enable USB1 in S5
S3U0, 8, // 0x22 - Enable USB0 in S3
S3U1, 8, // 0x23 - Enable USB1 in S3
+ TACT, 8, // 0x24 - Thermal Active trip point
+ TPSV, 8, // 0x25 - Thermal Passive trip point
+ TCRT, 8, // 0x26 - Thermal Critical trip point
+ DPTE, 8, // 0x27 - Enable DPTF
/* Base addresses */
Offset (0x30),
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-03 08:42:52 +0000