diff options
Diffstat (limited to 'src/soc/intel/baytrail/acpi.c')
| -rw-r--r-- | src/soc/intel/baytrail/acpi.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 89ab929bdd..1ab1eb3748 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -22,6 +22,7 @@ #include <arch/acpigen.h> #include <arch/io.h> #include <arch/smp/mpspec.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <console/console.h> @@ -39,6 +40,9 @@ #include <baytrail/pattrs.h> #include <baytrail/pmc.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> + #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \ @@ -74,6 +78,32 @@ static acpi_cstate_t cstate_map[] = { } }; +void acpi_init_gnvs(global_nvs_t *gnvs) +{ + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + + /* Top of Low Memory (start of resource allocation) */ + gnvs->tolm = nc_read_top_of_low_memory(); + +#if CONFIG_CONSOLE_CBMEM + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + +#if CONFIG_CHROMEOS + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); +#if CONFIG_EC_GOOGLE_CHROMEEC + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif +#endif +} + static int acpi_sci_irq(void) { const unsigned long actl = ILB_BASE_ADDRESS + ACTL; |