diff options
Diffstat (limited to 'src/soc/intel/baytrail/Kconfig')
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index e96b53d321..94ed887d5c 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -38,16 +38,11 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR - select ROMCC_BOOTBLOCK config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/baytrail/bootblock/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xe0000000 @@ -97,14 +92,9 @@ config MRC_RMT # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE # | MRC usage | # | | -# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE -# | Stack | -# | | | -# | v | -# +-------------+ -# | ^ | -# | | | -# | CAR Globals | +# -------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE +# | coreboot | +# | usage | # +-------------+ DCACHE_RAM_BASE # # Note that the MRC binary is linked to assume the region marked as "MRC usage" @@ -130,6 +120,10 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n |