diff options
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 37 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/fspcar.c | 32 |
3 files changed, 3 insertions, 67 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 45414a4c88..0505de9865 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_APOLLOLAKE bool + select INTEL_CAR_CQOS help Intel Apollolake support @@ -13,6 +14,7 @@ config SOC_INTEL_GEMINILAKE select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select IDT_IN_EVERY_STAGE select PAGING_IN_CACHE_AS_RAM + select INTEL_CAR_NEM help Intel GLK support @@ -60,6 +62,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_DSP @@ -295,40 +298,6 @@ config NHLT_RT5682 default n help Include DSP firmware settings for headset codec. - -choice - prompt "Cache-as-ram implementation" - default CAR_CQOS if !SOC_INTEL_GEMINILAKE - default CAR_NEM - help - This option allows you to select how cache-as-ram (CAR) is set up. - -config CAR_NEM - bool "Non-evict mode" - select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM - help - Traditionally, CAR is set up by using Non-Evict mode. This method - does not allow CAR and cache to co-exist, because cache fills are - block in NEM mode. - -config CAR_CQOS - bool "Cache Quality of Service" - select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_CQOS - help - Cache Quality of Service allows more fine-grained control of cache - usage. As result, it is possible to set up portion of L2 cache for - CAR and use remainder for actual caching. - -config USE_APOLLOLAKE_FSP_CAR - bool "Use FSP CAR" - select FSP_CAR - help - Use FSP APIs to initialize & tear down the Cache-As-Ram. - -endchoice - # # Each bit in QOS mask controls this many bytes. This is calculated as: # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index fc4dad7bb8..778811e5de 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -10,7 +10,6 @@ subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c bootblock-y += ../common/block/cpu/pm_timer_emulation.c -bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += car.c bootblock-y += heci.c bootblock-y += gspi.c diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c deleted file mode 100644 index 931b418fa7..0000000000 --- a/src/soc/intel/apollolake/fspcar.c +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <FsptUpd.h> - -const FSPT_UPD temp_ram_init_params = { - .FspUpdHeader = { - .Signature = 0x545F4450554C5041ULL, /* 'APLUPD_T' */ - .Revision = 1, - .Reserved = {0}, - }, - .FsptCommonUpd = { - .Revision = 0, - .Reserved = {0}, - /* - * It is a requirement for firmware to have Firmware Interface Table - * (FIT), which contains pointers to each microcode update. - * The microcode update is loaded for all logical processors before - * cpu reset vector. - * - * All SoC since Gen-4 has above mechanism in place to load microcode - * even before hitting CPU reset vector. Hence skipping FSP-T loading - * microcode after CPU reset by passing '0' value to - * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. - */ - .MicrocodeRegionBase = 0, - .MicrocodeRegionLength = 0, - .CodeRegionBase = - (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), - .CodeRegionLength = (uint32_t)CONFIG_ROM_SIZE, - .Reserved1 = {0}, - }, -}; |