3 files changed, 3 insertions, 22 deletions

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index d23f31c20b..c5a3547e6a 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -347,25 +347,6 @@ config CONSOLE_UART_BASE_ADDRESS
 	default 0xddffc000
 	depends on INTEL_LPSS_UART_FOR_CONSOLE
 
-config APL_SKIP_SET_POWER_LIMITS
-	bool
-	default n
-	help
-	  Some Apollo Lake mainboards do not need the Running Average Power
-	  Limits (RAPL) algorithm for a constant power management.
-	  Set this config option to skip the RAPL configuration.
-
-config APL_SET_MIN_CLOCK_RATIO
-	bool
-	depends on !APL_SKIP_SET_POWER_LIMITS
-	default n
-	help
-	  If the power budget of the mainboard is limited, it can be useful to
-	  limit the CPU power dissipation at the cost of performance by setting
-	  the lowest possible CPU clock. Enable this option if you need smallest
-	  possible CPU clock. This setting can be overruled by the OS if it has an
-	  p-state driver which can adjust the clock to its need.
-
 # M and N divisor values for clock frequency configuration.
 # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 0228cd2527..46fc904b6c 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -321,7 +321,7 @@ static void soc_init(void *data)
 	 */
 	p2sb_unhide();
 
-	if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
+	if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) {
 		printk(BIOS_INFO, "Skip setting RAPL per configuration\n");
 	} else {
 		config = config_of_soc();
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index e8920174a3..79a69f518c 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -79,11 +79,11 @@ void soc_core_init(struct device *cpu)
 	enable_pm_timer_emulation();
 
 	/* Set Max Non-Turbo ratio if RAPL is disabled. */
-	if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
+	if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) {
 		cpu_set_p_state_to_max_non_turbo_ratio();
 		/* Disable speed step */
 		cpu_set_eist(false);
-	} else if (CONFIG(APL_SET_MIN_CLOCK_RATIO)) {
+	} else if (CONFIG(SOC_INTEL_SET_MIN_CLOCK_RATIO)) {
 		cpu_set_p_state_to_min_clock_ratio();
 		/* Disable speed step */
 		cpu_set_eist(false);