diff options
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/p2sb.h | 25 |
2 files changed, 28 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ead6bf3f03..f9c62282ff 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> #include <intelblocks/systemagent.h> @@ -54,12 +55,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) bootblock_systemagent_early_init(); - dev = PCH_DEV_P2SB; - /* BAR and MMIO enable for PCR-Space, so that GPIOs can be configured */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + p2sb_enable_bar(); + p2sb_configure_hpet(); /* Decode the ACPI I/O port range for early firmware verification.*/ dev = PCH_DEV_PMC; diff --git a/src/soc/intel/apollolake/include/soc/p2sb.h b/src/soc/intel/apollolake/include/soc/p2sb.h new file mode 100644 index 0000000000..01ba7ffd24 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/p2sb.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_P2SB_H_ +#define _SOC_P2SB_H_ + +/* PCI config space registers */ +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0xB0 + +#endif /* _SOC_P2SB_H_ */ |