3 files changed, 11 insertions, 8 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index cc516f32ad..1323f573d1 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -351,4 +351,14 @@ config APL_SKIP_SET_POWER_LIMITS
 	  Limits (RAPL) algorithm for a constant power management.
 	  Set this config option to skip the RAPL configuration.
 
+# M and N divisor values for clock frequency configuration.
+# These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
+	hex
+	default 0x25a
+
+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
+	hex
+	default 0x7fff
+
 endif
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
index b2b1bb8623..bf8b9d74e3 100644
--- a/src/soc/intel/apollolake/include/soc/uart.h
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -18,13 +18,6 @@
 #ifndef _SOC_APOLLOLAKE_UART_H_
 #define _SOC_APOLLOLAKE_UART_H_
 
-/*
-* M and N divisor values for clock frequency configuration.
-* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
-*/
-#define CLK_M_VAL	0x025a
-#define CLK_N_VAL	0x7fff
-
 /* Initialize the console UART including the pads for the configured UART. */
 void pch_uart_init(void);
 
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
index 4c143ad854..d3c1b0d0ca 100644
--- a/src/soc/intel/apollolake/uart_early.c
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -69,6 +69,6 @@ void pch_uart_init(void)
 	gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
 
 	/* Program UART2 BAR0, command, reset and clock register */
-	uart_common_init(uart, base, CLK_M_VAL, CLK_N_VAL);
+	uart_common_init(uart, base);
 
 }